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Configuring the Spartan-6 FPGA
2012-05-29Publicerad av Sven-Åke Andersson
Spartan-6 FPGAs store the customized configuration data in SRAM-type internal latches. The number of configuration bits is between 3Mb and 33Mb depending on the device size and user-design implementation options. The configuration storage is volatile and must be reloaded whenever the FPGA is powered up. This storage can also be reloaded at any time by pulling the PROGRAM_B pin low (pressing the push button SW3). Several methods and data formats for loading configurations are available. For this to work the configuration data must be stored in the on-board SPI flash. This tutorial will show how to program the SPI flash.
Bit-serial configurations can either be master serial mode, where the FPGA generates the configuration clock (CCLK) signal, or slave serial mode, where the external configuration data source also clocks the FPGA. The available JTAG pins use boundary-scan protocols to load bit serial configuration data. The bitstream configuration information (download.bit) is generated by the ISE software using a program called BitGen.
The Xilinx ISE PROMGen software takes an FPGA bitstream (.bit) file as input and, with the appropriate options, generates a memory image file for the data array of an SPI serial flash. The output memory image file format is chosen through a PROMGen software command-line option. Typical file formats include Intel Hex (.mcs) and Motorola Hex (.exo).
Note: Throughout this document, the word configuration applies to downloading a bitstream to the FPGA whereas the word programming applies to downloading a flash image to the on-board serial flash.
Internal configuration process
The configuration process typically executes the following sequence:
- Detects power-up (power-on reset) or PROGRAM_B when low.
- Clears the whole configuration memory
- Samples the mode pins to determine the configuration mode, master or slave, bit-serial or parallel.
- Loads the configuration data starting with the bus-width detection pattern followed by a synchronization word, checks for the proper device code and ends with a cyclic redundancy check (CRC) of the complete bitstream.
- Starts a user-defined seuence of events: realising the internal reset of flip-flops, optionally waiting for the DCMs and/or PLLs to lock, activating the output drivers, and transitioning the DONE pin to high.
Internal configuration interfaces
The Master Serial Peripheral Interface (SPI) and the Master Byte-wide Peripheral Interface (BPI) are two common methods used for configuring the FPGA. The Spartan-6 FPGA configures itself from a directly attached industry-standard SPI serial flash PROM. The Spartan-6 can also configure itself via a BPI when connected to an industry-standard parallel NOR flash. Note that BPI configuration is not supported in the XC6LX4, XC6SLX25, and XC6LX25T nor is BPI available when using Spartan-6 FPGAs in TQG114 and CPG196 packages.
Configuring the Spartan-6 upon power-up
The Spartan-6 FPGA is pre-set to Master Serial Mode, which means it initiates configuration upon power-up and generates a configuration clock. It reads configuration data from an on-board Serial Flash memory. This flash can be programmed through either of the two aforementioned interfaces. This tutorial will illustrate how to use these interfaces to configure the FPGA and program the on-board serial flash.
SPI x4 flash
The Xilinx Spartan-6 FPGA hosts a SPI interface which is visible to the Xilinx iMPACT configuration tool. The SPI memory device operates at 3.0V; the Spartan-6 FPGA I/Os are 3.3V tolerant and provide electrically compatible logic levels to directly access the SPI flash through a 2.5V bank. The FPGA is a master device when accessing an external SPI flash memory device. The SP605 SPI interface has two parallel connected configuration options: an SPI X4 (Winbond W25Q64VSFIG) 64-Mb flash memory device (U32) and a flash programming header (J17). J17 supports a user-defined SPI mezzanine board. The SPI configuration source is selected via SPI select jumper J46.
Master SPI Dual and Quad read commands
The Master SPI configuration mode in Spartan-6 FPGAs supports the SPI flash memory dual (x2) and quad bit (x4) memory read commands. To enable this configuration method in software, the BitGen spi_buswidth option is used to create a .bit file for SPI x2 or x4. The FPGA still initially boots in x1 mode and then switches to x2 or x4 mode. For more information see document Xilinx UG380 Spartan-6 FPGA Configuration User Guide.
Here is a description on how to change from x1 to x4 memory read command. We will run the bitgen command in batch mode. First we have to edit the file bitgen.ut. We will add the following line: -g SPI_buswidth:4
--> cd ..../implementation
--> gedit bitgen.ut
--> bitgen -w -f bitgen.ut system
This command generates the file system.bit. We can now startup XPS and execute the <Download Bitstream> command which will generate a new download.bit file for us. Here is the printout from iMPACT when using the new download.bit file. This time the programming is running in x4 mode.
Programming the SPI flash through JTAG
We will use iMPACT to transfer the bitstream file to the SPI flash. Here is the setup. To program the SPI flash we need to convert the bitstream file to a Flash PROM image. We can use the program promgen to do that, but the first time we will use iMPACT for the complete flow. Let's start iMPACT.
--> impact &
We will create a new project.
We will prepare a PROM file.
We will use the SPI flash as our storage target.
The SPI flash is 64 MB.
Specify output file name and format (MCS).
Start adding configuration files.
We will add the download.bit file.
Start generating the PROM file.
We now have a prom file we can use to program the SPI flash. Let's restart iMPACT.
Right-click the SPI/BPI symbol and add the PROM file.
Select the SPI flash type.
Specify what is going to happen during the programmimh phase.
Program the flash.
The flash programming will take a couple of minutes to finish.
Preparing for power-up booting
We will set the configuration mode to Master Serial/SPI: M[1:0] = 01
Set the left switch (M0) in the upper position and push the SW3 push button.
We should see the following display on the attached terminal. The first stage bootloader is running.