Implementing a Nios II embedded processor system


2012-04-03Publicerad av Sven-Åke Andersson

Introduction


Going from one blinking LED to an emedded system using the Nios II soft processor is a big step. Are we ready to take this step. Let's find out.

Building an embedded system


Altera has two tools that helps us build an embedded system from scratch. They are called SOPC Builder and Qsys. Altera recommends using Qsys, the next-generation system integration tool, for new designs. Qsys provides many advantages over SOPC Builder, including higher performance with the new Qsys interconnect and faster development with support for hierarchical designs.
 

Altera Megafunctions


Altera and Altera Megafunction Partners Program (AMPPSM) partners offer a broad portfolio of megafunctions optimized for Altera devices. The Altera MegaCore functions and AMPP megafunctions are reusable blocks of intellectual property (IP) that we can customize and use in a design, allowing us to concentrate on adding proprietary value. Using megafunctions reduces our system implementation and verification times while maintaining high quality. With Altera's free OpenCore Plus evaluation feature, we can perform the following actions:

  • Simulate the behavior of a megafunction within our system
  • Verify the functionality of our design, as well as evaluate its size and speed quickly and easily
  • Generate time-limited device programming files for designs that include megafunctions
  • Program a device and verify our design in hardware

OpenCore Plus hardware evaluation supports the following two modes of operation:

  • Untethered—the design runs for a limited time
  • Tethered—requires a connection between your board and the host computer. If tethered mode is supported by all megafunctions in a design, the device can operate for a longer time or indefinitely.

We need to purchase a license for the megafunction only when we are completely satisfied with its functionality and performance, and want to take our design to production. Read more here.

Nios II 3C120 Design Example


We will start by studying this example from the Altera Wiki. This is a hardware design example for the Altera 3C120 development board. This board is currently available in many different bundled packages today that go by these names:

  • Cyclone III FPGA Development Kit (our board)
  • DSP Development Kit, Cyclone III Edition
  • Embedded Systems Development Kit, Cyclone III Edition

Any one of the above development kits should contain the 3C120 base board that this example design is intended to run on.The primary features of this system when built with the "development" option include the following:

  • Nios II/f CPU, with 32KB I cache and 32KB D cache
  • Low Latency DDR2 Interface, 128MB
  • High Latency DDR2 Interface, 128MB
  • External CFI Flash Interface, 64MB
  • System Timer
  • Altera TSE MAC subsystem with associated SGDMAs
  • Additional Timers, PIOs and UARTs
  • Separate Nios II/e controlled display subsystem which manages the 2 line LCD display, 128x64 graphic display and the user seven segment display


 

Nios II Non MMU 125MHz design


This is an updated version of the 10.1sp1 version into the 11.0sp1 tools release. This is a non-mmu version of the 11.0sp1 version of this project. The only difference between this version and the original 11.0sp1 port is that the Nios II processor in this system is built without the MMU. This design is not appropriate for linux development, however it is quite useful for non-linux development. Here is some more information about the system.

Build the hardware example


To build this hardware example download the file: 20110828_nommu_nios2_linux_3c120_125mhz_11.0sp1.tgz, extract the archive, change directory into the build_scripts directory and run: ./create-this-project.sh

Two things had to be fixed before we could run the script:

  1. Change the version control. We have installed Quartus 11.1 SP2. The script was setup to use 11.0 SP1. By changing this line in the create-this-project script we manage to pass the version control. I am not sure if this is OK. EXPECTED_QUARTUS_VERSION="Version 11.1 Build 259"
  2. Add the following path to the $PATH variable: PATH=/opt/Altera/11.1sp2/quartus/sopc_builder/bin:$PATH

Here is the result after the script has finished.



Configure the FPGA


We start Quartus and load our new design.



 
When we select the programmer the following window pops up.

 


 
It seems we have tethered OpenCore Plus IP licenses and as long as we have the board connected to our host computer we will have a working system.

 
 


OpenCore Plus Status


After we have configured the FPGA, this small but very important window pops up. The first time I did'nt understand the meaning of this message and clicked the Cancel button. This was not a good idea. It means we can't use the OpenCore IPs in our design anymore. This window must stay up all the time to enable us to use our design.
 


 

Next step


What is the next step. How do we get something up and running?. Read the next chapter.