ISim HDL simulator

2012-02-09Publicerad av Sven-Åke Andersson


The ISE Simulator ISim is the only HDL simulator available to us. Is it as good as the Mentor ModelSim and the Cadence IUS? Let's find out.


We will start out by downloading the ISim User Guide. The Xilinx ISE Simulator (ISim) is a Hardware Description Language (HDL) simulator that enables us to perform functional (behavioral) and timing simulations for VHDL, Verilog and mixed-language designs. This ISE Simulator environment is comprised of the following key elements:
  • vhpcomp (VHDL parser)
  • vlogcomp (Verilog parser)
  • fuse (HDL elaborator and linker)
  • Simulation executable
  • isimgui (Isim graphical user interface)

vhpcomp, vlogcomp

vhpcomp and vlogcomp parse and compile VHDL and Verilog source files respectively. The parsed dump generated by the parsers is used by fuse to generate object code and link object code with simulation kernel library to create a simulation executable.


The fuse command is the Hardware Description Language (HDL) elaborator and linker used by ISim. fuse effects static elaboration on the design given the top design units and then compiles the design units to object code. The design unit object files are then linked together to create a simulation executable. The fuse command can automatically invoke vlogcomp and vhpcomp for each VHDL or Verilog source code in a project file (.prj), allowing you to compile sources "on-the-fly".

Simulation executable

The Simulation Executable is generated by the fuse command. To run the simulation of a design in ISim, the generated simulation executable needs to be invoked. When ISim is run inside the ISE Project Navigator interface, ISE takes care of invoking the generated simulation executable. A command-line user needs to explicitly invoke the generated simulation executable to effect simulation. The simulation executable effects event-driven simulation and has rich support for driving and probing simulation using Tcl.


isimgui is the ISim Graphical User Interface. It contains the wave window, toolbars, panels, and the status bar. In the main window, you can view the simulation-visible parts of the design, add and view signals in the wave window, utilize ISim commands to run simulation, examine the design, and debug as necessary.

ISim Operating Modes

The simulator can be used in three different operating modes:

  • Graphical User Interface Mode
  • Interactive Command Line Mode
  • Batch Run Mode

The ISim simulator can run inside the ISE Project Navigator or as a stand-alone tool. In the first step we will use it as a stand-alone simulator.

Creating a simulation environment

When we install the GRLIB design environment from Aeroflex Gaisler all the design and simulation files resides in the same directory structure. I have decided to create a simulation environment outside the design directory looking like this. Separating the design and simulation activities make it easier to change or add more testcases without disturbing the design setup.


Copying files

The following files were copied from the design directory:

  • testbench.vhd
  • testbench_stx_beh.prj (used as a template for our three prj files)
  • prom.srec
  • sdram.srec
  • sram.srec

Defining an environment variable

To make it easier to move files around we will define an environment variable pointing to our CoreX project directory.

export COREX_HOME=/opt/home/svan/projects/CoreX

Compiling verilog files

In the project file <testbench_sim_vlog.prj> we add all the verilog design files. It looks like this:

The code will be compiled into the libraries defined in the project file. By default all the libraries will be put in the isim subdirectory.  We use the following command to compile all verilog files:

-> vlogcomp -work isim_temp -prj testbench_sim_vlog.prj.


Modifying the testbench

We have to make the following modifications to the testbench.vhd file.

Change micron to work (verilog files can only be compiled into work)


Compiling VHDL files

In the project file <testbench_sim_vhd.prj> we add all the VHDL design files and testbench files. The start looks like this:


The code will be compiled into the libraries defined in the project file. By default all the libraries will be put in the isim subdirectory.  We use the following command to compile all the VHDL files:

-> vhpcomp -work isim_temp -prj testbench_sim_vhd.prj


Simulation flow

The basic steps for simulating our design in ISim are as follows:

  • Gathering files and mapping libraries
  • Parsing and elaborating the design and test bench
  • Simulating the design
  • Examining the design
  • Debugging the design

Mapping of libraries

ISim uses the file <xilinxsim.ini> to map the default libraries to physical locations.  The compilers attempt to read xilinxsim.ini from these locations in the following order:

  1. $XILINX/vhdl/hdp/<platform>.
  2. User file specified through the -initfile switch in vlogcomp, vhpcomp or fuse.
  3. If -initfile is not specified, "xilinxsim.ini" in the current working directory is searched for.

The default mapping file can be found here: </opt/Xilinx/13.2/ISE_DS/ISE/vhdl/hdp/lin64>. The mapping looks like this:



These directories are read only and should not be modifed by us. Don't use any of these libraries to put our compiled code in.

Compilation and elaboration

We will start by creating a project file (testbench_sim_all.prj) where we put all the VHDL and Verilog design and testbench files. We use the following command to compile and elaborate the design and testbench:

-> fuse isim_temp.testbench -prj testbench_sim_all.prj -L esa -L eth -L gaisler -L grlib -L isim_temp -L opencores -L techmap -o test.exe


Here is the result after compilation and elaboration. The code will be compiled into libraries defined in the project file. By default all the libraries will be put in the isim subdirectory. The executable code is stored in test.exe


Running a simulation

Use the following command to start the simulation:

-> ./test.exe -tclbatch tcl/run_test

 The tcl command file (run_test) looks like this:


The simulation will run forever or until an error occur. We can break the simulation at any time using ctrl-c.


Debugging the design

The best way to debug our design is to use a waveform viewer and look at the waveform plot file generated during the simulation phase. The waveform file default name is isim.wdb. Use the following command to open the file in the ISim waveform viewer:

-> isimgui -view isim.wdb


For more information about the waveform viewer read the ISim User Guide chapter 6 (Waveform Analysis).

Using a wave configuration file

The default wave configuration file (Default.wcfg) will display all signals in the design. We can select the signals we would like to look at and save it to new wave configuration file. Select the signals and then Save As from the File menu:


To start isimgui with the new wavefrom configuration file use the following command:

-> isimgui -view isim.wdb -open leon3_signals1.wcfg

Ignore the following error message (it is a bug in Design Suite 13.2) and the wavform will be displayed showing only the signals in the waveform configuration file.