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LEON3 32-bit processor core
2012-01-31Publicerad av Sven-Åke Andersson
The LEON3 is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture developed by Aeroflex Gaisler AB in Sweden. The model is highly configurable, and particularly suitable for system-on-a-chip (SOC) designs. The full source code is available under the GNU GPL license, allowing free and unlimited use for research and education. LEON3 is also available under a low-cost commercial license, allowing it to be used in any commercial application to a fraction of the cost of comparable IP cores. The LEON3 processor has the following features:
- SPARC V8 instruction set with V8e extensions
- Advanced 7-stage pipeline
- Hardware multiply, divide and MAC units
- High-performance, fully pipelined IEEE-754 FPU
- Separate instruction and data cache (Harvard architecture) with snooping
- Configurable caches: 1 - 4 ways, 1 - 256 kbytes/way. Random, LRR or LRU replacement
- Local instruction and data scratch pad RAM, 1 - 512 Kbytes
- SPARC Reference MMU (SRMMU) with configurable TLB
- AMBA-2.0 AHB bus interface
- Advanced on-chip debug support with instruction and data trace buffer
- Symmetric Multi-processor support (SMP)
- Power-down mode and clock gating
- Robust and fully synchronous single-edge clock design
- Up to 125 MHz in FPGA and 400 MHz on 0.13 um ASIC technologies
- Fault-tolerant and SEU-proof version available for space applications
- Extensively configurable
- Large range of software tools: compilers, kernels, simulators and debug monitors
- High Performance: 1.4 DMIPS/MHz, 1.8 CoreMark/MHz (gcc -4.1.2)
IP cores from Aeroflex Gaisler
Aeroflex Gaisler develops VHDL IP cores using a novel high-level design methodology. Most cores are distributed as part of the GRLIB IP Library, providing an integrated SoC development platform. Based on the AMBA bus standard, the GRLIB IP library contains advanced high-quality cores such as the LEON3 SPARC processor, LEON4 SPARC processor, a fully pipelined double-precision IEEE-754 floating point unit, a 32-bit master/target PCI core with DMA and FIFOs, memory controllers, SpaceWire codec with RMAP support, 10/100/1000 Mbit ethernet MAC, USB host and device controllers, CAN controllers, timer, interrupt controller, UART, VGA controller, PS/2 interface, GPIO, AES cryptography and many more.
GRLIB IP library
The GRLIB IP Library is an integrated set of reusable IP cores, designed for system-on-chip (SOC) development. The IP cores are centered around the common on-chip bus, and use a coherent method for simulation and synthesis. The library is vendor independent, with support for different CAD tools and target technologies. A unique plug&play method is used to configure and connect the IP cores without the need to modify any global resources.
The complete design environment for LEON3 including all the IP cores can be downloaded from the download page. Before you use the GPL version of LEON3/GRLIB, please make sure that you read and understand the GPL license. Answers to common licensing questions can be found at the license FAQ section. GRLIB is distributed as a zipped file and can be installed in any location on the host system. We will download and install the file grlib_gpl-1.1.0-b4112.zip. Here is the result after unzipping.
GRLIB is organized around VHDL libraries, where each major IP (or IP vendor) is assigned a unique library name. Using separate libraries avoids name clashes between IP cores and hides unnecessary implementation details from the end user. Each VHDL library typically contains a number of packages, declaring the exported IP cores and their interface types. Simulation and synthesis scripts are created automatically by a global makefile. Adding and removing of libraries and packages can be made without modifying any global files, ensuring that modification of one vendor’s library will not affect other vendors. A few global libraries are provided to define shared data structures and utility functions.
GRLIB provides automatic script generators for the Modelsim, Ncsim, Aldec, Sonata and GHDL simulators, and the Synopsys, Synplify, Cadence, Mentor, Actel, Altera, Lattice, and Xilinx implementation tools. Support for other CAD tools can be easily be added.
The GRLIB is designed to be ‘bus-centric’, i.e. it is assumed that most of the IP cores will be connected through an on-chip bus. The AMBA-2.0 AHB/APB bus has been selected as the common on-chip bus, due to its market dominance (ARM processors) and because it is well documented and can be used for free without license restrictions. The figure below shows an example of a LEON3 system designed with GRLIB:
For more information about LEON3 read the IP user's manual. Now we are ready to implement our first design using the LEON3 processor.
Service and support
The Aeroflex Gaisler team offers support to assist in the creation of successful LEON-based products. Their design team has the skills and experience on projects ranging from feasibility studies to complex multi-processor SoC developments. Aeroflex Gaisler also maintains two email lists for those interested in the open-source LEON processor. The lists are hosted on YahooGroups, and include a searchable archive.
- leon_sparc is a general list discussing all aspects of LEON utilisation, synthesis and software development.
- leon_announce is a read-only list announcing new LEON releases or bug fixes.