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LEON3 quick start guide
2012-02-01Publicerad av Sven-Åke Andersson
This chapter will provide a simple quick-start guide on how to implement a LEON3 system using GRLIB. Refer to chapters 3 - 6 in the GRLIB user's guide for a deeper understanding of the GRLIB organization.
Implementing a LEON3 system is typically done using one of the template designs in the design directory. We will use the LEON3 template design for the Xilinx SP605 board.
Implementation is typically done in five basic steps:
- Configuration of the design using xconfig
- Simulation of design and test bench
- Synthesis and place&route
- Generate bitstream
- Configure the FPGA on the board
The template design is located in designs/leon3-xlinix-sp605, and is based on three files:
- config.vhd - a VHDL package containing design configuration parameters. Automatically generated by the xconfig GUI tool.
- leon3mp.vhd - contains the top level entity and instantiates all on-chip IP cores. It uses config.vhd to con- figure the instantiated IP cores.
- testbench.vhd - test bench with external memory, emulating the SP605 board.
Each core in the template design is configurable using VHDL generics. The value of these generics is assigned from the constants declared in config.vhd, created with the xconfig GUI tool.
Change directory to designs/leon3-xilinx-sp605 and issue the command ‘make xconfig’ in a bash shell. This will launch the xconfig GUI tool that can be used to modify the leon3 template design. When the configuration is saved and xconfig is exited, the config.vhd is automatically updated with the selected configuration. Here are some examples from the LEON3MP design configuration.
Here is an example from the UART, timer, I/O and interupt controller configuration window.
Click OK, save and exit. A new config file has been saved.
Generate the Xilinx memory control block
The design uses the Xilinx Memory Controller Block (MCB) with an AHB-2.0 interface. The MCB source code cannot be distributed due to the prohibitive Xilinx license, so the MCB must be re-generated with the Xilinx Memory Interface generator (MIG) before simulation and synthesis can be done.
To generate the MCB and install the Xilinx unisim simulation library, do as follows:
This will ONLY work with ISE Design Suite installed, and the XILINX environment variable properly set in the shell.
Synthesize the design
To synthesize the design use the following make command:
The synthesis starts and after a few seconds it stops with the following error report. We are having a problem.
We could try to fix it ourselves but why not try the Gaisler support page at Yahoo. I will post the error report and see how long it takes before we get an answer.
It didn't take more than a couple of hours berfore I had an answer. Good work by Jan at Gaisler. We will add the following line of code in the file leon3mp.vhd: use.gaisler.i2c.all;
The Xilinx design flow
When we rerun the make file it runs without problems. For more information about the Xilinx design flow, see document "Command Line Tools User Guide". Here are the steps included in the design flow.
1. Synthesis using Xilinx XST.
Here is the result after syntheis.
2. The build phase using NGDBuild.
NGDBuild reads in a netlist file in EDIF or NGC format and creates a Xilinx Native Generic Database (NGD) file that contains a logical description of the design in terms of logic elements, such as AND gates, OR gates, LUTs, flip-flops, and RAMs. The NGD file contains both a logical description of the design reduced to Xilinx primitives and a description of the original hierarchy expressed in the input netlist. The output NGD file can be mapped to the desired device family.
3. Mapping the design using MAP.
The MAP program maps a logical design to a Xilinx FPGA. The input to MAP is an NGD file, which is generated using the NGDBuild program. The NGD file contains a logical description of the design that includes both the hierarchical components used to develop the design and the lower level Xilinx primitives. MAP first performs a logical DRC (Design Rule Check) on the design in the NGD file. MAP then maps the design logic to the components (logic cells, I/O cells, and other components) in the target Xilinx FPGA. The output from MAP is an NCD (Native Circuit Description) file a physical representation of the design mapped to the components in the targeted Xilinx FPGA.
4. Place and route the design using the PAR program.
After we create a Native Circuit Description (NCD) file with the MAP program, we can place and route that design file using PAR. PAR accepts a mapped NCD file as input, places and routes the design, and outputs an NCD file to be used by the bitstream generator (BitGen).
5. Static timing analysis using the TRACE program.
The Timing Reporter And Circuit Evaluator (TRACE) tool provides static timing analysis of an FPGA design based on input timing constraints. TRACE performs two major functions:
- Timing Verification - Verifies that the design meets timing constraints.
- Reporting - Generates a report file that lists compliance of the design against the input constraints.
lHere is the result. We meet the 60MHz clock requirement.
6. Bitstream generation using BitGen.
BitGen is a Xilinx command line tool that generates a bitstream for Xilinx device configuration. After the design is completely routed, you configure the device using files generated by BitGen. BitGen takes a fully routed Native Circuit Description (NCD) file as input and produces a configuration Bitstream (BIT) file as output. A BIT file is a binary file with a .bit extension.
Configure the FPGA
We use the following make command to configure the Spartan-6 FPGA: