1.13 Modifying the LEON3 design

2012-02-22Publicerad av Sven-Åke Andersson


So far we have used the template design as is. Now it is time to build our own design and start modifying the SP605 board template design. We will start by changing the processor system clock speed. We can get some information from the README.txt file found in the design directory.


Here we can see that the AHB and processor are clocked by a 60MHz clock generated from the 33MHZ SYSACE clock using a DCM. The digital clock manager (DCM) component implements a clock delay locked loop (DLL), a digital frequency synthesizer (DFS), and a digital phase shifter (DPS). We are going to change the clock frequency to 66MHz and we will use xconfig.

cd ..../design/leon3-xilinx-sp605
make xconfig


Click Clock generation.


 When we click the Help button we get the following information.

To get the 66MHz clock we multiply by 2 and divide by 1.  proc_clk = (33 x 2)/1 = 66MHz. We change the multiplication factor to 2 and the division factor to 1 and save and exit xconfig. A new config.vhd file will be generated.

Run Xilinx design flow

To synthesis, place and route and generate the bitstream run:

make ise

Configure the FPGA

Configure the Spartan-6 FPGA using the command:

make ise-prog-fpga

For more information see LEON3 quick start guide.


A simple benchmark program

We will modify our prime number calculation program to be used as a simple benchmark by adding a processor clock measurement. It will look like this:



Here is the result from the program execution using GRMON.



The excution time is exacly 10% faster. When the processor clock was 60MHz it took 0.33s.


Controlling the LEDs

There are four LEDs on the board that can be used in our design.

They are located here (16a). The left most LED is DS3 (led 0).


Looking in the SP605 master UCF file found on the USB flash drive we find that they are connected like this:


In our current design (leon3mp.vhd) the LEDs are connected to the following signals. After configuring the board the LEDs 0, 2 and 3 will light.

LED Signal Description
0 ndsuact Inverted DSU active (debug mode) indicator
1 dbgo error CPU error mode indicator
2 calib_done Calibration done signal from MIG DDR3 memory controller
3 lock PLL lock indicator


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