Nios II soft processor
Nios II is a 32-bit embedded-processor architecture designed specifically for the Altera family of FPGAs. Nios II incorporates many enhancements over the original Nios architecture, making it more suitable for a wider range of embedded computing applications, from DSP to system-control. Nios II is licensable for standard-cell ASICs through a third-party IP provider, Synopsys Designware. Through the Designware license, designers can port Nios-based designs from an FPGA-platform to a mass production ASIC-device.
This is the first part of the Nios II tutorial. The chapters should be read in date order, starting with the oldest. At the end of every chapter there are four links called TOP, NEXT, PREVIOUS and TOC. The TOP link takes you the top of the current chapter. The NEXT link takes you to the next chapter, the PREVIOUS link takes you to the previous chapter and the TOC link takes you to the table of contents page. You can also click the Modesty-CoreX label and then click "Table of contents" to get to TOC page.
Nios II processor core
The Nios II architecture describes an instruction set architecture (ISA). The ISA in turn necessitates a set of functional units that implement the instructions. A Nios II processor core is a hardware design that implements the Nios II instruction set and supports the functional units described in this document. The processor core does not include peripherals or the connection logic to the outside world. It includes only the circuits required to implement the Nios II architecture. For more information see the Altera web page.
The Nios II architecture defines the following functional units:
- Register file
- Arithmetic logic unit (ALU)
- Interface to custom instruction logic
- Exception controller
- Internal or external interrupt controller
- Instruction bus
- Data bus
- Memory management unit (MMU)
- Memory protection unit (MPU)
- Instruction and data cache memories
- Tightly-coupled memory interfaces for instructions and data
- JTAG debug module
Choosing a development board
Plus some literature. This is 2007 style when printing on paper was still popular.
The Cyclone III Development KIT CD contains the following information. Only readable from a Windows PC.
Development kit content
The Cyclone III FPGA Development Kit features:
- Cyclone III development board
- Cyclone III EP3C120F780 FPGA
- Embedded USB-Blaster circuitry allowing download of FPGA configuration files via the flash device or the host computer
- 256 megabytes (MB) of dual-channel DDR2 SDRAM with error correction code (ECC)
- 8 MB of synchronous SRAM
- 64 MB of flash memory
- 10/100/1000 Ethernet
- USB 2.0
Power and analog devices from Linear Technology
- Switching power supply LTM4601
- Switching and step-down regulators LT1931, LT3481, and LTC3418
- Analog-to-digital converter LTC2402
- LDO regulators LT1963 and LT1761
- 50-MHz and 125-MHz on-board oscillators
- SMA inputs/outputs
- I/Os for the two HSMC connectors
- Various buttons, switches, and indicators
- 128 x 64 graphics LCD
- 2-line x 16-character LCD
- Two HSMCs
- USB type B
- Three HSMC debug cards (two loop-back and a debug header)
The reference manual describes the hardware features of the Cyclone® III development board, including detailed pin-out information to enable you to create custom FPGA designs that interface with all components of the board. For information about setting up and powering up the Cyclone III development board and using the kit’s demo software, refer to the Cyclone III Development Kit User Guide.
A simple power-on test can be done any time.
- Plug the supplied 16V DC power supply into an AC power outlet and connect it to the board.
- Connect the development board to your computer using the supplied USB cable.
- Turn on the development board power by pressing the power switch SW1. You should observe the following:
- The power LED is on and the Conf_Done LED is on.
- The eight user LEDs are counting up and down.
Installing the Altera design suite software
We will install the latest verison of the Altera design suite for Linux from the software download page.
Quartus II Web Edition Software
This is a free, no license required version of the Quartus II software for medium-density FPGA. Hopefully it will work for us.
Download the software
We will download the Linux version of the software (11.1sp2_259_quartus_free_linux.sh).
Installing the software
Let's start by reading the Installation Guide. Not much information was found there. We will just give it a try.
sudo bash ./11.1sp2_259_quartus_free_linux.sh
And what to install.
Modifying the PATH variable
Source the .profile and start the Quartus II design tool using the following command:
To get rid of the message "warning: setlocale: LC_CTYPE: cannot change locale (en_US): No such file or directory" run the following command:
Altera Quartus II help
The Quartus II development software provides a complete design environment for system-on-a-programmable-chip (SOPC) design. The Quartus II software ensures easy design entry, fast processing, and straightforward device programming. This web page describe the general capabilities and design flows of the Quartus II software.
JTAG cable driver setup
The Cyclone III development board includes an embedded USB-Blaster circuitry (in an Altera MAX II CPLD) allowing download of FPGA configuration files via the flash device or the host computer. We only have to connect a standard USB cable between the host computer and the board. Quartus II software uses the built-in usb device drivers on Linux to access the USB-Blaster download cable. To enable the usb device driver for the USB-Blaster we will add the following file in the directory: /etc/udev/rules.d We must have system administration (root) privileges to add the file.
After connecting the board to the computer we can use the command lsusb to display information about USB buses in the system and the devices connected to them.
Connecting to the board
When the USB cable is connected and identified we select the Programmer from the Tools menu in the Quartus GUI.
Click the Hardware Setup button and select the USB-Blaster device.
The FPGA will be detected and we are ready to configure the device.
In the next chapter we will build a configuration file for a simple design and try out the complete design flow. Welcome to join us.
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Altera support center
Here is a link to the Altera support center on the web.