OpenRISC 1200 soft processor


2012-03-02Publicerad av Sven-Åke Andersson

Introduction


The OpenRISC 1200 (OR1200) is a synthesizable CPU core maintained by developers at OpenCores.org. The OR1200 design is an open source implementation of the OpenRISC 1000 RISC architecture. The Verilog RTL description is released under the GNU Lesser General Public License (LGPL). For more information see OpenRisc 1200 Specification document or go to the OpenRISC 1200 IP Core Specification page.

Since  the 1st of November 2007 OpenCores is maintained by ORSoC. For a long period of time ORSoC has worked closely to OpenCores, both with the community and with development of the technology.

Reading instructions


This is the first part of the OpenRISC tutorial. The chapters should be read in date order, starting with the oldest. At the end of every chapter there are four links called TOP,  NEXT,  PREVIOUS and TOC. The TOP link takes you the top of the current chapter. The NEXT link takes you to the next chapter, the PREVIOUS link takes you to the previous chapter and the TOC link takes you to the table of contents page. You can also click the Modesty-CoreX label and then click Index to get to TOC page.
 
 



A review of the OpenRISC architecture and implementation


Julius Baxter has written a great review of open source development and especially the OpenRISC project in his master's thesis. It starts like this:

This document is a look at both the technical aspects of a microprocessor project and open source development. The technology involved in microprocessors and the philosophy and practices of open source development are first explained, before the OpenRISC project, a project combining the two, is presented. This project is then evaluated and the results of the development effort and the role open source has played are discussed. Read it here.


OpenRISC community portal
 

This wiki is the main entrance to information about the OpenRISC project. It has a lot of useful information about the development process. It took me a long time to find this page. Please add a link on the opencores.org site.

 

Architecture


The IP core of the OR1200 is implemented in the Verilog HDL. As an open source core, the design is fully public and may be downloaded and modified by any individual. The official implementation is maintained by developers at OpenCores.org. The implementation specifies a power management unit, debug unit, tick timer, programmable interrupt controller (PIC), central processing unit (CPU), and memory management hardware. Peripheral systems and a memory subsystem may be added using the processor's implementation of a standardized 32-bit Wishbone bus interface.

CPU/DSP


The OR1200 CPU is an implementation of the 32-bit ORBIS32 instruction set architecture (ISA) and (optionally) ORFP32X ISA implementing IEEE-754 compliant single precision floating point support. The ISA has five instruction formats and supports two addressing modes: register indirect with displacement, and PC-relative. The implementation has a single-issue 5-stage pipeline and is capable of single cycle execution on most instructions. The CPU also contains a MAC unit in order to better support digital signal processing (DSP) applications.



 
Default caches are 1-way direct-mapped 8KB data cache and 1-way direct-mapped 8KB instruction cache, each with 16-byte line size. Both caches are physically tagged. By default MMUs are implemented and they are constructed of 64-entry hash based 1-way direct-mapped data TLB and 64-entry hash based 1-way direct-mapped instruction TLB. Supplemental facilities include debug unit for real-time debugging, high resolution tick timer, programmable interrupt controller and power management support. For more information see: http://opencores.org/openrisc,or1200
 

General Microarchitecture

 
  • Central CPU/DSP block
  • IEEE 754 compliant single precision FPU
  • Direct mapped data cache
  • Direct mapped instruction cache
  • Data MMU based on hash-based DTLB
  • Instruction MMU based on hash-based ITLB
  • Power management unit and power management interface
  • Tick timer
  • Debug unit and development interface
  • Interrupt controller and interrupt interface
  • Instruction and Data WISHBONE B3 compliant interfaces



ORPSoC - OpenRISC Reference Platform SoC


ORPSoC is the OpenRISC Reference Platform System-on-Chip. This project implements a platform for OpenRISC development. It provides a reference SoC, primarily for the testing and development of OpenRISC processors, and a set of pre-built SoCs for various FPGA boards.
 

Downloading ORPSoC


The RTL source, test software and scripts can be downloaded from the OpenRISC project subversion (svn) repository. The sources can be checked out with the following command:

 svn co http://opencores.org/ocsvn/openrisc/openrisc/trunk/orpsocv2

 After unpacking the ORPSoC installation looks like this.

 



 

GNU toolchain


The GNU Toolchainis a blanket term for a collection of programming tools produced by the GNU Project.These tools form a toolchain (suite of tools used in a serial manner) used for developing applications and operating systems. The GNU toolchain plays a vital role in development of Linux kernel, BSD, and software for embedded systems.

Before we can start using ORPSoC platform we have to download and install the OpenRISC GNU newlib toolchain. The link on the GNU tooolchain web page doesn't work for some reason, but the GNU toolchain can be downloaded from this OpenCores FTP site:  ftp://ocuser:ocuser@openrisc.opencores.org/toolchain/or32-elf-1.0rc1-x86.tar.bz2

Here is a link to download the latest version of the toolchain. Observe, not exactly the same installation as described here below.


Newlib library


The OpenRISC 1000 port of the newlib library aims to provide a library to provide support for running on bare-metal hardware without an operating system. It is also used when running the GNU toolchain regression suite. The library is linked when using the newlib version of the GCC compiler (or32-elf-gcc) and adding the -mnewlib option. The target board is specified by -mboardname. If not board is specified, the default (-mor1ksim) is suitable for use with Or1ksim simulator.


GNU toolchain installation


The programs must be installed in the /opt directory. Use the following commands to unzip and unpack the downloaded file:

cd /opt
sudo tar xjf ...../or32-elf-1.0rc1-x86.tar.bz2 


Add the following symbolic links which helps when switching to new updated version later on :

sudo ln -s or32-elf-1.0rc1 or32-elf
sudo ln -s or1ksim-0.5.1rc1 or1ksim


Add the following path to the PATH varable in your .profile file:

PATH=/opt/or32-elf/bin:/opt/or1ksim/bin:$PATH

 



 

Installing in a Linux 64 bits system


When installing the GNU toolchain (32 bits Linux) in Debian Squeeze (64bits) the following i386 (32bits) libraries were missing:

  • libmpfr.so.1
  • libmpc.so.2
  • libgmp.so.3

Finding and installing these i386 libraries in an amd64 system is not that simple. Can anyone explain for me how to do it. One problem is that there are 64 bits versions of some of these libraries installed already.

Building the toolchain yourself
 

There is now a script environment called orbuild that can be downloaded and used to build the toolchain from source. For more information see Using orbuild.


Choosing a development board


From the installation we can see that there are support for a number of development boards. We look for a board with a SPARTAN-6 FPGA and find the Digilent Atlys board. Let's give it a try. I will order the board at once.
 

The MinSoC project


The Minimal OpenRISC System on Chip (minsoc) is a system on chip (SoC) implementation with standard IP cores available at OpenCores. This implementation consists of a standard project comprehending the standard IP cores necessary for a SoC embedding the OpenRISC implementation OR1200.

This project idea is to offer a synthesizable SoC which can be uploaded to every FPGA and be compatible with every FPGA board without the requirement of changing its code. In order to deliver such a project, the project has been based on a standard memory implementation and the Advanced Debug System, which allows system debug and software upload with the same cables used for FPGA configuration.

 

Getting help


If we need help with the development we can post to the OpenRISC forum or send an email to openrisc_team@opencores.org. There are also four mailing list you can subscribe to. It seems most of the discussion about OpenRISC takes place in these mailing lists. A pattern of usage seems to be emerging, where general users ask their questions on the OpenRISC forum, while developers discuss new design ideas and post patches on the four mailing lists. Click the first link to subscribe to the list and click the second link to send an email to the list.
 


IRC


Most of the regular contributors can be found on channel #opencores at freenode.net. They are a friendly bunch, and a good source of advice.
 

Links


Here are links to companies using the OpenRISC processor and to other interesting information about the OpenRISC processor. 

AntMicro
ÅAC Microtec Wiki

EMBECOSM
ORSoC
Beginners' Guide to OpenRISC