1.3 The SP605 evaluation board
The SP605 board enables hardware and software developers to create or evaluate designs targeting the Spartan-6 XC6SLX45T-3FGG484 FPGA. For more information read the document "SP605 Hardware User Guide UG 526" found on the USB flash drive.
The Spartan-6 family
The Spartan-6 family provides system integration capabilities with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous Spartan families, and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input look-up table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIOTM technology, power-optimized high-speed serial transceiver blocks, PCI Express compatible Endpoint blocks, advanced system-level power management modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protection.
Spartan-6 FPGA feature summary
This figure shows a high-level block diagram of the SP605 and its peripherals.
This figure shows a board photo with numbered features corresponding to table here below.
|1||Spartan-6 FPGA||ZC6SLX45T-3FGG484 FPGA|
|2||DDR3 Memory||Micron MT41J64M16LA-187E|
|3||SPI Header Ext. x4||Winbond W25Q64VSFIG|
|4||Linear BPI Flash x16||Numonyx JS28F256P30T95|
|5||SystemACE CompactFlash Socket||XCCACE-TQ144I Controller|
|6||USB JTAG Connector (USB Mini-B)||USB JTAG Download Circuit|
|7||Clock generation||200 MHz Osc|
|8||GTP port SMA x4||MGT RX, TX Pairs x4 SMA MGT REFCLK x2 SMA|
|9||PCIe 1-lane edge connector||Card Edge Connector 1-lane|
|10||SPF Module Cage/Connector||AMP 136073-1|
|11||Ethernet 10/100/1000||Marwell M88E1111 EPHY|
|12||USB UART||Silicon Labs CP2103GM|
|13||DVI Codec and Video Connector||Chrontel CH7301C-TF|
|14||IIC EEPROM (on backside)||ST Micro M24C08-WDW6TP|
|16||User LEDs, pushbuttons, DIP switches|
|18||FMC LPC Connector||Samtec ASP-134603-01|
|19||Power Management||2 x TI UCD9240PFC|
The typical Xilinx FPGA power up and configuration status LEDs are present on the SP605. The red INIT LED DS17 comes on momentarily after the FPGA powers up and during its internal power-on process. The DONE LED DS2 comes on after the FPGA programming bitstream has been downloaded and the FPGA successfully configured.
Configuring the SP605 board
The SP605 supports configuration in the following modes:
- JTAG (using the included USB-A to Mini-B cable)
- JTAG (using System ACE CF and CompactFlash card)
- Master SPI x4
- Master SPI x4 with off-board device
- Linear BPI Flash
USB JTAG configuration
JTAG configuration is provided through onboard USB-to-JTAG configuration logic where a computer host accesses the SP605 JTAG chain through a Type-A (computer host side) to Type-Mini-B (SP605 side) USB cable. The JTAG chain of the board is illustrated in figure below. JTAG configuration is allowable at any time under any mode pin setting. JTAG initiated configuration takes priority over the mode pin settings. We will start configuring the Spartan-6 FPGA using JTAG.
We will use iMPACT to check if we can access the SP605 board and make sure we have the Digilent drivers installed. Let's start iMPACT.
We will create a new project.
and configure the device using Boundary-Scan (JTAG)
The boundary-scan chain is identified and the devices connected are displayed in the iMPACT tool. We can start configuring the FPGA any time we want.