SP605 MIG example design


2012-01-31Publicerad av Sven-Åke Andersson

Introduction


Before we start our real design we will run an example design provided by Xilinx to familirize ourselves with the Xilinx design tools (ISE, ChipScope and Core Generator). The example design can be found on the USB flash drive in the directory SP605_Reference_Designs and is called SP605_MIG_rdf0029.



 
 

Memory Interface Generator


Memory Interface Generator
(MIG) is a free software tool used to generate memory controllers and interfaces for Xilinx® FPGAs. MIG generates unencrypted Verilog or VHDL design files, UCF constraints, simulation files and implementation script files to simplify the design process. Memory Interfaces supported are: DDR3 SDRAM, DDR2 SDRAM, QDRII SRAM, and DDRII SRAM, LP DDR, QDRII+ SRAM, and RLDRAM II.
 

Documentation


Let's download the documentation (sp605_MIG_pdf_xtp060_13.2_c.pdf). The pdf file contains a description of the whole design flow.


 


 


 Here is an overview of the Memory Controller Block (MCB) creation flow using the Memory Interface Generator.

 
 
 


Running Xilinx Core Generator



Start coregen and follow the detailed description in the document to generate the Spartan-6 memory controller block.

 


 
 



See the document for many more steps.

 

 

Here are some of the files that were generated.
 


 
 

Here are all the files that were generated from the coregen run.
 




 

Modification to the example design
 

Copy the file sp605_MIG_rdf0029-13.2_c.zip from the USB flash drive to the directory sp605_mig_design and unzip the file. This will add the modifications described in the document to the example design.
 


 


Generate the bitstream


We will use the ISE run script  ise_flow.sh to run the complete bitstream generation flow in batch mode. We may have to change the first line in the script to:  #!/bin/sh -f  if we use bash instead of csh.






Configure the Spartan-6 FPGA
 

We are ready to configure the FPGA on the SP605 board.
 

 
 

Using ChipScope Pro


ChipScope Pro tool inserts logic analyzer, system analyzer, and virtual I/O low-profile software cores directly into our design, allowing us to view any internal signal or node, including embedded hard or soft processors. Signals are captured in the system at the speed of operation and brought out through the programming interface, freeing up pins for our design. Captured signals are then displayed and analyzed using the ChipScope Pro Analyzer tool. We will use ChipScope Pro to configure the FPGA and then look a waveforms on the memory bus.

Start ChipScope from the terminal using the command: analyzer.

 
 


Click the on Open Cable button to identify the boundary-scan chain and the devices connected to the chain.

 

 

Select configuration file


From the Device menu select DEV1 MyDevice1 (XC6SLX45T) -> Configure and use the file example_top.bit as the bitstream file.



 

Follow the dokument to setup trigger conditions and start a waveform capture.


 

 

Conclusion


I think we have got a good understanding of the SP605 evaluation board and how it can be used. We are now ready to implementing our own design. Let's start by looking at the LEON3 soft processor.