Synopsys VCS simulator

2012-02-10Publicerad av Sven-Åke Andersson


Here is what Synopsys has to say about their VCS simulator. How much is true. Let's find out.

Industry-leading designers of today’s most advanced designs rely on the Synopsys VCS functional verification solution for their verification environments. In fact, 90% of designs at 32nm and below are verified with VCS. Used by a majority of the world’s top 20 semiconductor companies as their primary verification solution,VCS provides the high performance simulation engines, constraint solver engines, Native Testbench (NTB) support, broad SystemVerilog support, verification planning, coverage analysis and closure, and an integrated debug environment. VCS has continually pioneered numerous industry-first innovations, and is now poised to meet the challenges and complexity of today’s SoCs. With features such as constrained random testbench, SoC optimized compile flow, coverage, and assertions, VCS has the flexibility and capabilities that are critical for today’s SoC design and verification teams’ success.

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VCS MX is a compiled code simulator. It enables us to analyze,  compile, and simulate Verilog, VHDL, mixed-HDL, SystemVerilog,  OpenVera and SystemC design descriptions. It also provides us  with a set of simulation and debugging features to validate our  design. These features provide capabilities for source-level  debugging and simulation result viewing. VCS MX accelerates complete system verification by delivering fast and high capacity Verilog, VHDL, and mixed HDL  simulation for RTL functional verification.


Using the simulator

VCS MX uses the following three basic steps to compile, elaborate  and simulate any Verilog, VHDL, and mixed HDL designs:
  • Analyzing the design
  • Elaborating the design
  • Simulating the design

Analyzing the design

VCS MX provides us with the vhdlan and vlogan executables to  analyze our VHDL and Verilog design code. vhdlan/vlogan analyzes our design and stores the intermediate files in the design or a work library. By default, vhdlan is VHDL-93 compliant, and vlogan is Verilog-2000 compliant.

The vhdlan utility

The vhdlan utility analyzes VHDL source files and produces intermediate files for simulation. It checks for syntactic errors and if  it finds any, generates error messages for them. The vhdlan utility  uses the synopsys_sim.setup file to determine the logical-tophysical mapping of VHDL libraries.

--> vhdlan [vhdlan_options] VHDL_filename_list

Using smartorder

The smart_order option, with vhdlan, allows us to automatically identify the file order dependencies internally and then  do file by file analysis of all VHDL files passed to it, so that they are  ordered as per the dependencies of the design units contained within them.

The vlogan  utility

VCS MX uses the vlogan utility to analyze Verilog portions of a  design instantiated within a VHDL design. The syntax of the vlogan command line is as follows:
--> vlogan [vlogan_options] Verilog_source_file_name(s)

Creating a synopsys_sim.setup file

VCS MX uses the synopsys_sim.setup file to configure its  environment for VHDL and mixed-HDL designs. This file maps the  VHDL design library names to specific host directories, sets search  paths, and assigns values to simulation control variables. When you invoke VCS MX, it looks for the synopsys_sim.setup files in the following three directories with the same order:

Master setup directory

The synopsys_sim.setup file in the $VCS_HOME/bin directory contains default settings for our entire installation. VCS MX reads this file first.

Our home directory

VCS MX reads the setup file in our home directory second, if  present. The settings in this file take precedence over the  conflicting settings in our synopsys_sim.setup file in the master setup directory, and carry over the rest.

Our run directory

VCS MX reads the setup file in our design directory last. The settings in this file take precedence over the conflicting settings in our synopsys_sim.setup file in the master setup directory, and the synopsys_sim.setup file in our home directory, and will carry over the rest. We can use this file to customize the environment for a particular design. 

Default Time Unit and Time Precision

The default time unit for Verilog and SystemVerilog simulation is 1 ns. The default time precision for Verilog and SystemVerilog simulation is 1 ns. For VHDL simulation there is no concept of a default time unit and delay values. The default time precision for an entirely VHDL design is specified with the TIME_RESOLUTION 1 ns entry in the synopsys_sim.setup file in the VCS MX installation.

The default time precision for the VHDL part of a mixed HDL design is the smallest or finest of these two:

  • What is specified with the TIME_RESOLUTION entry in the synopsys_sim.setup.
  • The smallest time precision from the Verilog or SystemVerilog part of the design.
We  can override the default time precision with the -time_res elaboration option.