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Xilinx Platform Studio
2012-04-20Publicerad av Sven-Åke Andersson
Xilinx Platform Studio (XPS) enables hardware designers to create highly customized embedded processor systems and integrate those designs into Xilinx FPGAs. XPS is comprised of graphical design views and sophisticated wizards that guide the user through the steps necessary to create AXI and PLB based processor systems in minutes.
Available as part of the IDS Design Suite: Embedded Edition, XPS steps users through a logical progression of design steps allowing users to quickly create and customize single and multi-processor designs based on MicroBlaze™ or PowerPC®. New support for AXI based MicroBlaze can result in more optimized, higher performance system performance. Simulation support is completely automated, including support for the Xilinx ISim simulator. The debug wizard makes integration of ChipScope™ debug components easy, at any stage of project development. For more information about XPS and EDK read the document: EDK Concepts, Tools and Techniques.
Are we ready to use XPS. We will see. Here is the startup sequence:
Here is the startup screen.
Create a new project using Base System Builder
We will take the simple track and use the Base System Builder wizard and use the AXI interconnect type.
We select the Spartan-6 SP605 Evalution board and optimize for throughput.
Here is the system we are going to design. We enable the floating point unit and set the memory and caches to 32 KB. We also enable interrupt for all cores that have interrupt functionality. The uart baud-rate is set to 115 200. We remove all the IIC cores and add the axi_timer core.
When we click the Finish button the following system is generated.
Here is the memory and register mapping.
Fixing the AXI clock
For some strange reason the AXI clock is automatically set to half the speed of the processor clock. This is done during the system build and we didn't notice it. Having two different clock frequencies in system will make it larger and according to Göran Bilski (the father of MicroBlaze) there is no reason for having it that way. We will exit XPS and open the system.mhs file and change all AXI clock (S_AXI_ACLK) defintions like this:
The complete design flow
The Navigator window lists all activities needed to implement the design in the Spartan-6 FPGA.
Design rule check
The Design Rule Check (DRC) performs system-level design rule checks in XPS. When this command is performed, the Warnings and Errors tabs in the console are cleared to display the most recent design rule check messages. To check design rules, select: Project > Design Rule Checks, or click the Project DRC button.
When we generate the netlist, the platform building tool, Platgen is invoked, which does the following:
- Reads the design platform configuration MHS file and runs all necessary design rule checks to validate the correctness of the design.
- Synthesizes the design using Xilinx Synthesis Technology (XST).
- Produces netlist files (with an .ngc extension) for each peripheral, as well as the overall embedded system.
- Generates Hardware Description Language (HDL) wrapper files for each peripheral and the overall system. To see the created HDL files, look in the <project_name>\system\hdl directory.
The Generate Bitstream command generates the file that will be used to configure (program) the FPGA. The generated bitstream file is located in the \implementation folder of our project and is called system.bit. There is another file generated called system_bd.bmm, which Xilinx Software Development Kit (SDK) uses for loading memory onto our target board. We will use SDK for configuring our board.
The final result
Here is the file structure that has been generated.
Exporting to SDK
We will finish this session by exporting the design to SDK.
Nine month later
The MicroBlaze is now version 8.40b. Everything works fine, there is only one "strange thing" happening. These warnings appear during Design Rule Check:
WARNING:EDK:4180 - PORT: Interrupt_address_in, CONNECTOR: microblaze_0_interrupt_Interrupt_address_in - No driver found. Port will be driven to GND
WARNING:EDK:4181 - PORT: Processor_ack_out, CONNECTOR: microblaze_0_interrupt_Processor_ack_out - floating connection
I will find out from Xilinx what this is all about.